675 lines
32 KiB
C
675 lines
32 KiB
C
/**********************************************************************************************************************
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* COPYRIGHT
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* -------------------------------------------------------------------------------------------------------------------
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* \verbatim
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* Copyright (c) 2025 by Vector Informatik GmbH. All rights reserved.
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*
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* This software is copyright protected and proprietary to Vector Informatik GmbH.
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* Vector Informatik GmbH grants to you only those rights as set out in the license conditions.
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* All other rights remain with Vector Informatik GmbH.
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* \endverbatim
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* -------------------------------------------------------------------------------------------------------------------
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* FILE DESCRIPTION
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* -----------------------------------------------------------------------------------------------------------------*/
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/** \file File: ARMBrsHwIntTb_CortexR.c
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* Project: Vector Basic Runtime System
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* Module: BrsHw for all platforms with ARM core Cortex-R
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* Template: This file is reviewed according to Brs_Template@Implementation[1.03.12]
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*
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* \brief Description: This is a global, hardware-independent file for the ARM-BRS.
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* It consists of the core exception table for Startup and a 2nd one to be copied into RAM
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* for FBL projects.
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*
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* \attention Please note:
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* The demo and example programs only show special aspects of the software. With regard to the fact
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* that these programs are meant for demonstration purposes only, Vector Informatik liability shall be
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* expressly excluded in cases of ordinary negligence, to the extent admissible by law or statute.
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*********************************************************************************************************************/
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/**********************************************************************************************************************
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* REVISION HISTORY
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* -------------------------------------------------------------------------------------------------------------------
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* Refer to ARMBrsHw_CortexR.h.
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*********************************************************************************************************************/
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/**********************************************************************************************************************
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* EXAMPLE CODE ONLY
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* -------------------------------------------------------------------------------------------------------------------
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* This Example Code is only intended for illustrating an example of a possible BSW integration and BSW configuration.
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* The Example Code has not passed any quality control measures and may be incomplete. The Example Code is neither
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* intended nor qualified for use in series production. The Example Code as well as any of its modifications and/or
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* implementations must be tested with diligent care and must comply with all quality requirements which are necessary
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* according to the state of the art before their use.
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*********************************************************************************************************************/
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#define ARMBRSHWINTTB_CORTEXR_SOURCE
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/**********************************************************************************************************************
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* INCLUDES
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*********************************************************************************************************************/
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#include "ARMBrsHw_CortexR.h"
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/**********************************************************************************************************************
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* CONFIGURATION CHECK
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*********************************************************************************************************************/
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#if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
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#else
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#error "Unknown compiler specified!"
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#endif
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/**********************************************************************************************************************
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* PROTOTYPES OF LOCAL FUNCTIONS
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*********************************************************************************************************************/
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#if defined (BRS_FIRST_EXECUTION_INSTANCE)
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BRS_ISR_KEYWORD void BrsHw_CoreExceptionHandler(void);
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#endif
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#if defined (BRS_ENABLE_OS_MULTICORESUPPORT)
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BRS_ISR_KEYWORD void BrsHw_MultiCoreExceptionHandler(void);
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BRS_LOCAL_FUNCTION_PROTOTYPE(intvect_Core1Exceptions)
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# if (BRS_CPU_CORE_AMOUNT > 2)
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BRS_LOCAL_FUNCTION_PROTOTYPE(intvect_Core2Exceptions)
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# endif
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# if (BRS_CPU_CORE_AMOUNT > 3)
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BRS_LOCAL_FUNCTION_PROTOTYPE(intvect_Core3Exceptions)
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# endif
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# if (BRS_CPU_CORE_AMOUNT > 4)
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BRS_LOCAL_FUNCTION_PROTOTYPE(intvect_Core4Exceptions)
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# endif
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# if (BRS_CPU_CORE_AMOUNT > 5)
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BRS_LOCAL_FUNCTION_PROTOTYPE(intvect_Core5Exceptions)
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# endif
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# if (BRS_CPU_CORE_AMOUNT > 6)
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BRS_LOCAL_FUNCTION_PROTOTYPE(intvect_Core6Exceptions)
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# endif
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# if (BRS_CPU_CORE_AMOUNT > 7)
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BRS_LOCAL_FUNCTION_PROTOTYPE(intvect_Core7Exceptions)
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# endif
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# if (BRS_CPU_CORE_AMOUNT > 8)
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#error "More than 8 cores actually not supported by ARMBrsHwIntTb_CortexR.c!"
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# endif
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#endif /*BRS_ENABLE_OS_MULTICORESUPPORT*/
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#if defined (BRS_ENABLE_FBL_SUPPORT) && defined (BRS_FBL_EXCEPTIONTABLE_IN_RAM)
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BRS_ISR_KEYWORD void BrsHw_CoreExceptionHandler_Ram(void);
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#endif
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extern void brsStartupEntry(void);
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#if defined (BRS_FIRST_EXECUTION_INSTANCE)
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/* This code is only needed for the first instance/executable in the system */
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/********************************************************************************************
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* *
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* Startup Core Exception Handler *
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* *
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********************************************************************************************/
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#define BRS_START_SEC_STARTUP_CODE
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#include "Brs_MemMap.h"
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BRS_ISR_KEYWORD void BrsHw_CoreExceptionHandler(void)
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{
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#if defined (BRSHW_BRSHW_COREEXCEPTIONHANDLER_CALLOUT)
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BrsTestsuite_BrsHw_CoreExceptionHandler();
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#endif
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volatile uint8 Brs_Continue;
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Brs_Continue = 0;
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while (Brs_Continue == 0)
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{
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/* Set BrsMain_Continue to 1 to continue here.
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* If the debugger is not able to show the stack properly, this mechanism can be used to find the
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* source of the exception. */
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}
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}
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#define BRS_STOP_SEC_STARTUP_CODE
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#include "Brs_MemMap.h"
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/********************************************************************************************
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* *
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* Startup Core Exception Table *
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* *
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********************************************************************************************/
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# if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
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# pragma clang section text = ".brsExcVect"
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__attribute__((naked)) void intvect_CoreExceptions(void)
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{
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/* Exception Table */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 0: Reset */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 1: Undefined Instruction */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 2: SVCall */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 3: Abort Prefetch */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 4: Abort Data */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 5: Reserved */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 6: IRQ */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 7: FIQ */
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}
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# pragma clang section text = ""
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/* Exception Vectors */
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__attribute__((section(".brsExcVectConst"))) void (* const intvect_CoreExceptions_vectortable[])(void) = {
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brsStartupEntry, /* Exception 0: Reset */
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BrsHw_CoreExceptionHandler, /* Exception 1: Undefined Instruction */
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BrsHw_CoreExceptionHandler, /* Exception 2: SVCall */
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BrsHw_CoreExceptionHandler, /* Exception 3: Abort Prefetch */
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BrsHw_CoreExceptionHandler, /* Exception 4: Abort Data */
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BrsHw_CoreExceptionHandler, /* Exception 5: Reserved */
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BrsHw_CoreExceptionHandler, /* Exception 6: IRQ */
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BrsHw_CoreExceptionHandler /* Exception 7: FIQ */
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};
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/* Backup Exception Vectors */
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__attribute__((section(".brsExcVectConst"))) void (* const intvect_CoreExceptions_vectortable_backup[])(void) = {
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brsStartupEntry, /* Exception 0: Reset */
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BrsHw_CoreExceptionHandler, /* Exception 1: Undefined Instruction */
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BrsHw_CoreExceptionHandler, /* Exception 2: SVCall */
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BrsHw_CoreExceptionHandler, /* Exception 3: Abort Prefetch */
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BrsHw_CoreExceptionHandler, /* Exception 4: Abort Data */
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BrsHw_CoreExceptionHandler, /* Exception 5: Reserved */
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BrsHw_CoreExceptionHandler, /* Exception 6: IRQ */
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BrsHw_CoreExceptionHandler /* Exception 7: FIQ */
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};
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# endif /*BRS_COMP_LLVMDIAB||BRS_COMP_LLVMTEXASINSTRUMENTS*/
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#endif /*BRS_FIRST_EXECUTION_INSTANCE*/
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#if defined (BRS_ENABLE_OS_MULTICORESUPPORT)
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const ARMBrsHw_PhysicalCoreId_CoreExceptions_MappingType BrsHw_intvect_CoreExceptions_list[BRS_CPU_CORE_AMOUNT-1] = {
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{1, intvect_Core1Exceptions}
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# if (BRS_CPU_CORE_AMOUNT > 2)
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,{2, intvect_Core2Exceptions}
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# endif
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# if (BRS_CPU_CORE_AMOUNT > 3)
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,{3, intvect_Core3Exceptions}
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# endif
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# if (BRS_CPU_CORE_AMOUNT > 4)
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,{4, intvect_Core4Exceptions}
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# endif
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# if (BRS_CPU_CORE_AMOUNT > 5)
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,{5, intvect_Core5Exceptions}
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# endif
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# if (BRS_CPU_CORE_AMOUNT > 6)
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,{6, intvect_Core6Exceptions}
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# endif
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# if (BRS_CPU_CORE_AMOUNT > 7)
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,{7, intvect_Core7Exceptions}
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# endif
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};
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/********************************************************************************************
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* *
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* MultiCore Exception Handler *
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* *
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********************************************************************************************/
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#if defined (BRS_FIRST_EXECUTION_INSTANCE)
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#define BRS_START_SEC_STARTUP_CODE
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#include "Brs_MemMap.h"
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#endif
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BRS_ISR_KEYWORD void BrsHw_MultiCoreExceptionHandler(void)
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{
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#if defined (BRSHW_BRSHW_MULTICOREEXCEPTIONHANDLER_CALLOUT)
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BrsTestsuite_BrsHw_MultiCoreExceptionHandler();
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#endif
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volatile uint8 Brs_Continue;
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Brs_Continue = 0;
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while (Brs_Continue == 0)
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{
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/* Set Brs_Continue to 1 to continue here.
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* If the debugger is not able to show the stack properly, this mechanism can be used to find the
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* source of the exception. */
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}
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}
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#if defined (BRS_FIRST_EXECUTION_INSTANCE)
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#define BRS_STOP_SEC_STARTUP_CODE
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#include "Brs_MemMap.h"
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#endif
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/********************************************************************************************
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* *
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* Core 1 Exception Table *
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* *
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********************************************************************************************/
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# if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
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# pragma clang section text = ".brsExcVect1"
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__attribute__((naked)) void intvect_Core1Exceptions(void)
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{
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/* Exception Table */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 0: Reset */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 1: Undefined Instruction */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 2: SVCall */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 3: Abort Prefetch */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 4: Abort Data */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 5: Reserved */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 6: IRQ */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 7: FIQ */
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}
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# pragma clang section text = ""
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/* Exception Vectors */
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__attribute__((section(".brsExcVect1Const"))) void (* const intvect_Core1Exceptions_vectortable[])(void) = {
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brsStartupEntry, /* Exception 0: Reset */
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BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
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BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
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BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
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BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
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BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
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BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
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BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
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};
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/* Backup Exception Vectors */
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__attribute__((section(".brsExcVect1Const"))) void (* const intvect_Core1Exceptions_vectortable_backup[])(void) = {
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brsStartupEntry, /* Exception 0: Reset */
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BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
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BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
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BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
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BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
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BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
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BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
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BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
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};
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# endif /*BRS_COMP_LLVMDIAB||BRS_COMP_LLVMTEXASINSTRUMENTS*/
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# if (BRS_CPU_CORE_AMOUNT > 2)
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/********************************************************************************************
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* *
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* Core 2 Exception Table *
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* *
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********************************************************************************************/
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# if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
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# pragma clang section text = ".brsExcVect2"
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__attribute__((naked)) void intvect_Core2Exceptions(void)
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{
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/* Exception Table */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 0: Reset */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 1: Undefined Instruction */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 2: SVCall */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 3: Abort Prefetch */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 4: Abort Data */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 5: Reserved */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 6: IRQ */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 7: FIQ */
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}
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# pragma clang section text = ""
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/* Exception Vectors */
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__attribute__((section(".brsExcVect2Const"))) void (* const intvect_Core2Exceptions_vectortable[])(void) = {
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brsStartupEntry, /* Exception 0: Reset */
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BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
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BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
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BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
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BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
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BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
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BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
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BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
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};
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/* Backup Exception Vectors */
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__attribute__((section(".brsExcVect2Const"))) void (* const intvect_Core2Exceptions_vectortable_backup[])(void) = {
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brsStartupEntry, /* Exception 0: Reset */
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BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
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BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
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BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
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BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
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BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
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BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
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BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
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};
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# endif /*BRS_COMP_LLVMDIAB||BRS_COMP_LLVMTEXASINSTRUMENTS*/
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# endif /*BRS_CPU_CORE_AMOUNT > 2*/
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# if (BRS_CPU_CORE_AMOUNT > 3)
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/********************************************************************************************
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* *
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* Core 3 Exception Table *
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* *
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********************************************************************************************/
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# if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
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# pragma clang section text = ".brsExcVect3"
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__attribute__((naked)) void intvect_Core3Exceptions(void)
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{
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/* Exception Table */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 0: Reset */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 1: Undefined Instruction */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 2: SVCall */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 3: Abort Prefetch */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 4: Abort Data */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 5: Reserved */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 6: IRQ */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 7: FIQ */
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}
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# pragma clang section text = ""
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/* Exception Vectors */
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__attribute__((section(".brsExcVect3Const"))) void (* const intvect_Core3Exceptions_vectortable[])(void) = {
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brsStartupEntry, /* Exception 0: Reset */
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BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
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BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
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BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
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BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
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BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
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BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
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BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
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};
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/* Backup Exception Vectors */
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__attribute__((section(".brsExcVect3Const"))) void (* const intvect_Core3Exceptions_vectortable_backup[])(void) = {
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brsStartupEntry, /* Exception 0: Reset */
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BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
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BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
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BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
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BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
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BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
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BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
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BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
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};
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# endif /*BRS_COMP_LLVMDIAB||BRS_COMP_LLVMTEXASINSTRUMENTS*/
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# endif /*BRS_CPU_CORE_AMOUNT > 3*/
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# if (BRS_CPU_CORE_AMOUNT > 4)
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/********************************************************************************************
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* *
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* Core 4 Exception Table *
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* *
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********************************************************************************************/
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# if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
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# pragma clang section text = ".brsExcVect4"
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__attribute__((naked)) void intvect_Core4Exceptions(void)
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{
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/* Exception Table */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 0: Reset */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 1: Undefined Instruction */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 2: SVCall */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 3: Abort Prefetch */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 4: Abort Data */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 5: Reserved */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 6: IRQ */
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__asm(" ldr pc,[pc,#0x18] "); /* Exception 7: FIQ */
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}
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# pragma clang section text = ""
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/* Exception Vectors */
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__attribute__((section(".brsExcVect4Const"))) void (* const intvect_Core4Exceptions_vectortable[])(void) = {
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brsStartupEntry, /* Exception 0: Reset */
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BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
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BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
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BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
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BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
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BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
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BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
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BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
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};
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/* Backup Exception Vectors */
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__attribute__((section(".brsExcVect4Const"))) void (* const intvect_Core4Exceptions_vectortable_backup[])(void) = {
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brsStartupEntry, /* Exception 0: Reset */
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|
BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
|
|
BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
|
|
};
|
|
# endif /*BRS_COMP_LLVMDIAB||BRS_COMP_LLVMTEXASINSTRUMENTS*/
|
|
|
|
|
|
|
|
# endif /*BRS_CPU_CORE_AMOUNT > 4*/
|
|
|
|
# if (BRS_CPU_CORE_AMOUNT > 5)
|
|
/********************************************************************************************
|
|
* *
|
|
* Core 5 Exception Table *
|
|
* *
|
|
********************************************************************************************/
|
|
|
|
|
|
# if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
|
|
# pragma clang section text = ".brsExcVect5"
|
|
__attribute__((naked)) void intvect_Core5Exceptions(void)
|
|
{
|
|
/* Exception Table */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 0: Reset */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 1: Undefined Instruction */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 2: SVCall */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 3: Abort Prefetch */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 4: Abort Data */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 5: Reserved */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 6: IRQ */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 7: FIQ */
|
|
}
|
|
# pragma clang section text = ""
|
|
|
|
/* Exception Vectors */
|
|
__attribute__((section(".brsExcVect5Const"))) void (* const intvect_Core5Exceptions_vectortable[])(void) = {
|
|
brsStartupEntry, /* Exception 0: Reset */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
|
|
BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
|
|
};
|
|
|
|
/* Backup Exception Vectors */
|
|
__attribute__((section(".brsExcVect5Const"))) void (* const intvect_Core5Exceptions_vectortable_backup[])(void) = {
|
|
brsStartupEntry, /* Exception 0: Reset */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
|
|
BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
|
|
};
|
|
# endif /*BRS_COMP_LLVMDIAB||BRS_COMP_LLVMTEXASINSTRUMENTS*/
|
|
|
|
|
|
|
|
# endif /*BRS_CPU_CORE_AMOUNT > 5*/
|
|
|
|
# if (BRS_CPU_CORE_AMOUNT > 6)
|
|
/********************************************************************************************
|
|
* *
|
|
* Core 6 Exception Table *
|
|
* *
|
|
********************************************************************************************/
|
|
|
|
|
|
# if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
|
|
# pragma clang section text = ".brsExcVect6"
|
|
__attribute__((naked)) void intvect_Core6Exceptions(void)
|
|
{
|
|
/* Exception Table */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 0: Reset */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 1: Undefined Instruction */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 2: SVCall */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 3: Abort Prefetch */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 4: Abort Data */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 5: Reserved */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 6: IRQ */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 7: FIQ */
|
|
}
|
|
# pragma clang section text = ""
|
|
|
|
/* Exception Vectors */
|
|
__attribute__((section(".brsExcVect6Const"))) void (* const intvect_Core6Exceptions_vectortable[])(void) = {
|
|
brsStartupEntry, /* Exception 0: Reset */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
|
|
BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
|
|
};
|
|
|
|
/* Backup Exception Vectors */
|
|
__attribute__((section(".brsExcVect6Const"))) void (* const intvect_Core6Exceptions_vectortable_backup[])(void) = {
|
|
brsStartupEntry, /* Exception 0: Reset */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
|
|
BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
|
|
};
|
|
# endif /*BRS_COMP_LLVMDIAB||BRS_COMP_LLVMTEXASINSTRUMENTS*/
|
|
|
|
|
|
|
|
# endif /*BRS_CPU_CORE_AMOUNT > 6*/
|
|
|
|
# if (BRS_CPU_CORE_AMOUNT > 7)
|
|
/********************************************************************************************
|
|
* *
|
|
* Core 7 Exception Table *
|
|
* *
|
|
********************************************************************************************/
|
|
|
|
|
|
# if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
|
|
# pragma clang section text = ".brsExcVect7"
|
|
__attribute__((naked)) void intvect_Core7Exceptions(void)
|
|
{
|
|
/* Exception Table */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 0: Reset */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 1: Undefined Instruction */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 2: SVCall */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 3: Abort Prefetch */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 4: Abort Data */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 5: Reserved */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 6: IRQ */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 7: FIQ */
|
|
}
|
|
# pragma clang section text = ""
|
|
|
|
/* Exception Vectors */
|
|
__attribute__((section(".brsExcVect7Const"))) void (* const intvect_Core7Exceptions_vectortable[])(void) = {
|
|
brsStartupEntry, /* Exception 0: Reset */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
|
|
BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
|
|
};
|
|
|
|
/* Backup Exception Vectors */
|
|
__attribute__((section(".brsExcVect7Const"))) void (* const intvect_Core7Exceptions_vectortable_backup[])(void) = {
|
|
brsStartupEntry, /* Exception 0: Reset */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
|
|
BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
|
|
BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
|
|
};
|
|
# endif /*BRS_COMP_LLVMDIAB||BRS_COMP_LLVMTEXASINSTRUMENTS*/
|
|
|
|
|
|
|
|
# endif /*BRS_CPU_CORE_AMOUNT > 7*/
|
|
#endif /*BRS_ENABLE_OS_MULTICORESUPPORT*/
|
|
|
|
#if defined (BRS_ENABLE_FBL_SUPPORT) && defined (BRS_FBL_EXCEPTIONTABLE_IN_RAM)
|
|
/********************************************************************************************
|
|
* *
|
|
* Core Exception Handler in RAM *
|
|
* *
|
|
********************************************************************************************/
|
|
#define BRS_START_SEC_RAM_CODE
|
|
#include "Brs_MemMap.h"
|
|
BRS_ISR_KEYWORD void BrsHw_CoreExceptionHandler_Ram(void)
|
|
{
|
|
#if defined (BRSHW_BRSHW_COREEXCEPTIONHANDLER_RAM_CALLOUT)
|
|
BrsTestsuite_BrsHw_CoreExceptionHandler_Ram();
|
|
#endif
|
|
|
|
volatile uint8 Brs_Continue;
|
|
Brs_Continue = 0;
|
|
|
|
while (Brs_Continue == 0)
|
|
{
|
|
/* Set Brs_Continue to 1 to continue here.
|
|
* If the debugger is not able to show the stack properly, this mechanism can be used to find the
|
|
* source of the exception. */
|
|
}
|
|
}
|
|
#define BRS_STOP_SEC_RAM_CODE
|
|
#include "Brs_MemMap.h"
|
|
|
|
/********************************************************************************************
|
|
* *
|
|
* Core Exception Table in RAM *
|
|
* *
|
|
********************************************************************************************/
|
|
# if !defined (BRS_FIRST_EXECUTION_INSTANCE)
|
|
#error "If this executable is not first execution instance, reset vector must be manually set in RAM exception table to entry address!"
|
|
/* Replace brsStartupEntry in the RAM exception table with, e.g., 0x80, as this linker symbol will not exist in this case. Then, comment out the error message above. */
|
|
# endif
|
|
|
|
|
|
|
|
# if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
|
|
# pragma clang section text = ".brsExcVectRam"
|
|
__attribute__((naked)) void intvect_CoreExceptions_Ram(void)
|
|
{
|
|
/* Exception Table */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 0: Reset */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 1: Undefined Instruction */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 2: SVCall */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 3: Abort Prefetch */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 4: Abort Data */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 5: Reserved */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 6: IRQ */
|
|
__asm(" ldr pc,[pc,#0x18] "); /* Exception 7: FIQ */
|
|
}
|
|
# pragma clang section text = ""
|
|
|
|
/* Exception Vectors */
|
|
__attribute__((section(".brsExcVectRamConst"))) void (* const intvect_CoreExceptions_Ram_Vectortable[])(void) = {
|
|
brsStartupEntry, /* Exception 0: Reset */
|
|
BrsHw_CoreExceptionHandler_Ram, /* Exception 1: Undefined Instruction */
|
|
BrsHw_CoreExceptionHandler_Ram, /* Exception 2: SVCall */
|
|
BrsHw_CoreExceptionHandler_Ram, /* Exception 3: Abort Prefetch */
|
|
BrsHw_CoreExceptionHandler_Ram, /* Exception 4: Abort Data */
|
|
BrsHw_CoreExceptionHandler_Ram, /* Exception 5: Reserved */
|
|
BrsHw_CoreExceptionHandler_Ram, /* Exception 6: IRQ */
|
|
BrsHw_CoreExceptionHandler_Ram /* Exception 7: FIQ */
|
|
};
|
|
# endif /*BRS_COMP_LLVMDIAB||BRS_COMP_LLVMTEXASINSTRUMENTS*/
|
|
|
|
|
|
|
|
#endif /*BRS_ENABLE_FBL_SUPPORT&&BRS_FBL_EXCEPTIONTABLE_IN_RAM*/
|