113 lines
7.0 KiB
C
113 lines
7.0 KiB
C
|
/***********************************************************************************************************************
|
||
|
|
* FILE DESCRIPTION
|
||
|
|
* ------------------------------------------------------------------------------------------------------------------*/
|
||
|
|
/** \file
|
||
|
|
* \brief Register definitions for AWR1 and AWR2
|
||
|
|
*
|
||
|
|
* --------------------------------------------------------------------------------------------------------------------
|
||
|
|
* COPYRIGHT
|
||
|
|
* --------------------------------------------------------------------------------------------------------------------
|
||
|
|
* \par Copyright
|
||
|
|
* \verbatim
|
||
|
|
* Copyright (c) 2025 by Vector Informatik GmbH. All rights reserved.
|
||
|
|
*
|
||
|
|
* This software is copyright protected and proprietary to Vector Informatik GmbH.
|
||
|
|
* Vector Informatik GmbH grants to you only those rights as set out in the license conditions.
|
||
|
|
* All other rights remain with Vector Informatik GmbH.
|
||
|
|
* \endverbatim
|
||
|
|
*/
|
||
|
|
/**********************************************************************************************************************/
|
||
|
|
|
||
|
|
/***********************************************************************************************************************
|
||
|
|
* REVISION HISTORY
|
||
|
|
* --------------------------------------------------------------------------------------------------------------------
|
||
|
|
* Version Date Author Change Id Description
|
||
|
|
* --------------------------------------------------------------------------------------------------------------------
|
||
|
|
* 01.04.00 2020-12-21 visrie FBL-2517 Added support for AWR1
|
||
|
|
* 01.05.00 2021-01-28 visjdn FBL-2824 Added support for TPR12
|
||
|
|
* 01.06.00 2021-05-19 visjdn FBL-3038 No changes
|
||
|
|
* 01.07.00 2021-05-31 visjdn FBL-3545 No changes
|
||
|
|
* 01.08.00 2021-07-08 visjdn FBL-3694 No changes
|
||
|
|
* 01.09.00 2021-11-22 vistmo FBL-4275 No changes
|
||
|
|
* 01.10.00 2022-01-12 visjdn FBL-3720 No changes
|
||
|
|
* 01.11.00 2022-03-09 visrie FBL-4770 No changes
|
||
|
|
* 01.12.00 2022-07-18 visjdn FBL-5115 No changes
|
||
|
|
* 01.13.00 2023-02-09 fmenke FBL-6162 No changes
|
||
|
|
* ESCAN00113692 No changes
|
||
|
|
* 01.14.00 2023-04-20 jschmitding FBL-5733 No changes
|
||
|
|
* 01.15.00 2023-07-12 fmenke FBL-6966 No changes
|
||
|
|
* 01.16.00 2024-01-01 fmenke FBL-7559 No changes
|
||
|
|
* ESCAN00116504 No changes
|
||
|
|
* 01.17.00 2024-09-27 jschmitding FBL-9330 Add support Sitara AM263x
|
||
|
|
* 01.17.01 2024-10-22 visrie ESCAN00118141 No changes
|
||
|
|
* 01.18.00 2024-12-02 fmenke FBL-9747 No changes
|
||
|
|
* 01.19.00 2025-11-19 jostravsky FBL-11077 No changes
|
||
|
|
**********************************************************************************************************************/
|
||
|
|
|
||
|
|
#ifndef FBL_SFR_H
|
||
|
|
#define FBL_SFR_H
|
||
|
|
|
||
|
|
/***********************************************************************************************************************
|
||
|
|
* VERSION
|
||
|
|
**********************************************************************************************************************/
|
||
|
|
|
||
|
|
#if defined( FBL_SFR_BASE_ADRESSES_PRECONFIGURED )
|
||
|
|
#else
|
||
|
|
# error "Error in fbl_sfr.h: Please add base addresses for your derivative to the .pcu file."
|
||
|
|
#endif /* FBL_SFR_BASE_ADRESSES_PRECONFIGURED */
|
||
|
|
|
||
|
|
/* PRQA S 3453 TAG_SfrDefinitionMacros */ /* MD_MSR_FctLikeMacro */
|
||
|
|
|
||
|
|
#ifndef FBL_IOS
|
||
|
|
# define FBL_IOS(type, base, offset) (*((volatile type *)((base) + (offset))))
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* RTI Registers */
|
||
|
|
#define FBL_RTI_GCTRL FBL_IOS(vuint32, FBL_RTI_BASE, 0x0000uL) /** RTI Global Control */
|
||
|
|
#define FBL_RTI_TBCTRL FBL_IOS(vuint32, FBL_RTI_BASE, 0x0004uL) /** RTI Timebase Control */
|
||
|
|
#define FBL_RTI_CAPCTRL FBL_IOS(vuint32, FBL_RTI_BASE, 0x0008uL) /** RTI Capture Control */
|
||
|
|
#define FBL_RTI_COMPCTRL FBL_IOS(vuint32, FBL_RTI_BASE, 0x000CuL) /** RTI Compare Control */
|
||
|
|
#define FBL_RTI_FRC(x) FBL_IOS(vuint32, FBL_RTI_BASE, 0x0010uL + ((x) * 0x0020uL)) /** RTI Free Running Counter */
|
||
|
|
#define FBL_RTI_UC(x) FBL_IOS(vuint32, FBL_RTI_BASE, 0x0014uL + ((x) * 0x0020uL)) /** RTI Up Counter */
|
||
|
|
#define FBL_RTI_CPUC(x) FBL_IOS(vuint32, FBL_RTI_BASE, 0x0018uL + ((x) * 0x0020uL)) /** RTI Compare Up Counter */
|
||
|
|
#define FBL_RTI_CAFRC(x) FBL_IOS(vuint32, FBL_RTI_BASE, 0x0020uL + ((x) * 0x0020uL)) /** RTI Capture Free Running Counter */
|
||
|
|
#define FBL_RTI_CAUC(x) FBL_IOS(vuint32, FBL_RTI_BASE, 0x0024uL + ((x) * 0x0020uL)) /** RTI Capture Up Counter */
|
||
|
|
#define FBL_RTI_COMP(x) FBL_IOS(vuint32, FBL_RTI_BASE, 0x0050uL + ((x) * 0x0008uL)) /** RTI Compare */
|
||
|
|
#define FBL_RTI_UDCP(x) FBL_IOS(vuint32, FBL_RTI_BASE, 0x0054uL + ((x) * 0x0008uL)) /** RTI Update Compare */
|
||
|
|
#define FBL_RTI_INTFLAG FBL_IOS(vuint32, FBL_RTI_BASE, 0x0088uL) /** RTI Interrupt Flag */
|
||
|
|
#define FBL_RTI_CMPCLR(x) FBL_IOS(vuint32, FBL_RTI_BASE, 0x00B0uL + ((x) * 0x0004uL)) /** RTI Compare Clear */
|
||
|
|
|
||
|
|
#define FBL_RTI_TIMER_MS 0u /* Timer used for milliseconds */
|
||
|
|
#define FBL_RTI_TIMER_FREE 1u /* Timer used as free running */
|
||
|
|
#define FBL_RTI_GCTRL_TIMER_ENABLE 0x00000003uL /* Enable bits for timer 1 and 2 */
|
||
|
|
#define FBL_RTI_COMPCTRL_TIMER_SELECT 1uL /* Select bit for Compare0 */
|
||
|
|
|
||
|
|
/* GPIO handling */
|
||
|
|
#if defined( FBL_GIO_BASE )
|
||
|
|
# define FBLHW_ENABLE_GPIO_HANDLING
|
||
|
|
#else
|
||
|
|
# define FBLHW_DISABLE_GPIO_HANDLING
|
||
|
|
#endif /* FBL_GIO_BASE */
|
||
|
|
|
||
|
|
#if defined( FBLHW_ENABLE_GPIO_HANDLING )
|
||
|
|
/* GPIO Registers */
|
||
|
|
# define FBL_GIO_GCR FBL_IOS(vuint32, FBL_GIO_BASE, 0x0000uL) /** GIO reset */
|
||
|
|
# define FBL_GIO_WDN FBL_IOS(vuint32, FBL_GIO_BASE, 0x0004uL) /** GIO power down mode register */
|
||
|
|
# define FBL_GIO_DIR(x) FBL_IOS(vuint32, FBL_GIO_BASE, 0x0034uL + ((x) * 0x0020uL)) /** GIO data direction of pins */
|
||
|
|
# define FBL_GIO_DIN(x) FBL_IOS(vuint32, FBL_GIO_BASE, 0x0038uL + ((x) * 0x0020uL)) /** GIO data input for pins */
|
||
|
|
# define FBL_GIO_DOUT(x) FBL_IOS(vuint32, FBL_GIO_BASE, 0x003CuL + ((x) * 0x0020uL)) /** GIO data output for pins */
|
||
|
|
# define FBL_GIO_SET(x) FBL_IOS(vuint32, FBL_GIO_BASE, 0x0040uL + ((x) * 0x0020uL)) /** GIO data set */
|
||
|
|
# define FBL_GIO_CLR(x) FBL_IOS(vuint32, FBL_GIO_BASE, 0x0044uL + ((x) * 0x0020uL)) /** GIO data clear */
|
||
|
|
# define FBL_GIO_PDR(x) FBL_IOS(vuint32, FBL_GIO_BASE, 0x0048uL + ((x) * 0x0020uL)) /** GIO open drain */
|
||
|
|
# define FBL_GIO_PULDIS(x) FBL_IOS(vuint32, FBL_GIO_BASE, 0x004CuL + ((x) * 0x0020uL)) /** GIO pul disable */
|
||
|
|
# define FBL_GIO_PSL(x) FBL_IOS(vuint32, FBL_GIO_BASE, 0x0050uL + ((x) * 0x0020uL)) /** GIO pul select */
|
||
|
|
#endif /* FBLHW_ENABLE_GPIO_HANDLING */
|
||
|
|
|
||
|
|
/* PRQA L:TAG_SfrDefinitionMacros */
|
||
|
|
|
||
|
|
#endif /* FBL_SFR_H */
|
||
|
|
|
||
|
|
/***********************************************************************************************************************
|
||
|
|
* END OF FILE: FBL_SFR.H
|
||
|
|
**********************************************************************************************************************/
|