297 lines
14 KiB
C
297 lines
14 KiB
C
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/**********************************************************************************************************************
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* COPYRIGHT
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* -------------------------------------------------------------------------------------------------------------------
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* \verbatim
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* Copyright (c) 2025 by Vector Informatik GmbH. All rights reserved.
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*
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* This software is copyright protected and proprietary to Vector Informatik GmbH.
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* Vector Informatik GmbH grants to you only those rights as set out in the license conditions.
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* All other rights remain with Vector Informatik GmbH.
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* \endverbatim
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* -------------------------------------------------------------------------------------------------------------------
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* FILE DESCRIPTION
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* -----------------------------------------------------------------------------------------------------------------*/
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/** \file File: ARMBrsHw_CortexR.c
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* Project: Vector Basic Runtime System
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* Module: BrsHw for all platforms with ARM core Cortex-R
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* Template: This file is reviewed according to Brs_Template@Implementation[1.03.12]
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*
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* \brief Description: This is a global, platform-independent file for the ARM-BRS.
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* This file includes all non-platform dependent functions.
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* All the (platform depending) rest needs to be defined in BrsHw.c
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*
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* \attention Please note:
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* The demo and example programs only show special aspects of the software. With regard to the fact
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* that these programs are meant for demonstration purposes only, Vector Informatik liability shall be
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* expressly excluded in cases of ordinary negligence, to the extent admissible by law or statute.
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*********************************************************************************************************************/
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/**********************************************************************************************************************
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* REVISION HISTORY
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* -------------------------------------------------------------------------------------------------------------------
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* Refer to ARMBrsHw_CortexR.h.
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*********************************************************************************************************************/
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/**********************************************************************************************************************
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* EXAMPLE CODE ONLY
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* -------------------------------------------------------------------------------------------------------------------
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* This Example Code is only intended for illustrating an example of a possible BSW integration and BSW configuration.
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* The Example Code has not passed any quality control measures and may be incomplete. The Example Code is neither
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* intended nor qualified for use in series production. The Example Code as well as any of its modifications and/or
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* implementations must be tested with diligent care and must comply with all quality requirements which are necessary
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* according to the state of the art before their use.
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*********************************************************************************************************************/
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#define ARMBRSHW_CORTEXR_SOURCE
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/**********************************************************************************************************************
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* INCLUDES
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*********************************************************************************************************************/
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#include "BrsHw.h"
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#if !defined (BRS_DISABLE_OS_USAGE)
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/* BootManager, FlashBootLoader, HSM-Updater and HypervisorMaster execution instances do not use an OS. Define is set in BrsMain.h */
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#include "Os.h"
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#endif
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/**********************************************************************************************************************
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* VERSION CHECK
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*********************************************************************************************************************/
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#if (ARMBRSHW_CORTEXR_VERSION != 0x0205u)
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#error "Header and source file are inconsistent!"
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#endif
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#if (ARMBRSHW_CORTEXR_BUGFIX_VERSION != 0x05u)
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#error "Different versions of bugfix in Header and Source used!"
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#endif
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/**********************************************************************************************************************
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* CONFIGURATION CHECK
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*********************************************************************************************************************/
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#if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
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#else
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#error "Unknown compiler specified!"
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#endif
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#if !defined (BRSHW_ARMCOMMON_COREEXCEPTIONS_AT_ADDRESS_0) && !defined (BRS_FIRST_EXECUTION_INSTANCE)
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# if !defined (BRSHW_COREEXCEPTIONS_ADDRESS_OF_INIT_CORE)
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/* As intvect_CoreExceptions is not available within non-First-Execution-Instance binaries, it is necessary to
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hardly configure the address of intvect_CoreExceptions for your platform additionally.
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This is needed for the exception vector change within BrsHw_ExceptionTable_Init(). */
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#error "BRSHW_COREEXCEPTIONS_ADDRESS_OF_INIT_CORE needs to be defined in BrsHw.h of your platform!"
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# endif
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#endif
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#if (BRSMAIN_VERSION < 0x0221u)
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/* At least BrsMain 2.21.00 is needed for Hypervisor support and definition of BRS_DISABLE_OS_USAGE */
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#error "BrsMain of at least version 2.21.00 is needed for this BrsHw package!"
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#endif
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/**********************************************************************************************************************
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* DEFINITION + MACROS
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*********************************************************************************************************************/
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/**********************************************************************************************************************
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* GLOBAL VARIABLES
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*********************************************************************************************************************/
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/**********************************************************************************************************************
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* GLOBAL CONST VARIABLES
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*********************************************************************************************************************/
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/**********************************************************************************************************************
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* LOCAL VARIABLES AND LOCAL HW REGISTERS
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*********************************************************************************************************************/
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/**********************************************************************************************************************
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* CONTROLLER CONFIGURATION REGISTERS
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*********************************************************************************************************************/
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/**********************************************************************************************************************
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* LOCAL VARIABLES
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*********************************************************************************************************************/
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/**********************************************************************************************************************
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* LOCAL CONST VARIABLES
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*********************************************************************************************************************/
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/**********************************************************************************************************************
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* PROTOTYPES OF GLOBAL FUNCTIONS
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*********************************************************************************************************************/
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#if defined (BRS_FIRST_EXECUTION_INSTANCE)
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extern void intvect_CoreExceptions(void);
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#endif
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#if defined (BRS_ENABLE_OS_MULTICORESUPPORT)
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extern ARMBrsHw_PhysicalCoreId_CoreExceptions_MappingType BrsHw_intvect_CoreExceptions_list[BRS_CPU_CORE_AMOUNT-1];
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#endif
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/**********************************************************************************************************************
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* PROTOTYPES OF LOCAL FUNCTIONS
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*********************************************************************************************************************/
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/**********************************************************************************************************************
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* FUNCTION DEFINITIONS
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*********************************************************************************************************************/
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/*****************************************************************************/
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/* @brief Disable the global system interrupt.
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* @pre Must be the first function call in main@BrsMain
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* @param[in] -
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* @param[out] -
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* @return -
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* @context Function is called from main@BrsMain at power on initialization
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*****************************************************************************/
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void BrsHwDisableInterruptAtPowerOn(void)
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{
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/* Disable IRQ, FIQ */
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__asm(" MRS R0, CPSR "); /* Read CPSR Register */
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__asm(" ORR R0, R0, #0x040 "); /* Set Asynchronous FIQ Mask bit */
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__asm(" ORR R0, R0, #0x080 "); /* Set Asynchronous IRQ Mask bit */
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__asm(" MSR CPSR_c, R0 "); /* Write CPSR Register (only bits [7:0]) */
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#if defined (BRSHW_DISABLE_INTERRUPT_AT_POWERON_HOOK_AVAILABLE)
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/* used to configure additional, platform specific registers (e.g. VIC)
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BRSHW_DISABLE_INTERRUPT_AT_POWERON_HOOK_AVAILABLE to be defined in BrsHw.h */
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BrsHwDisableInterruptAtPowerOn_Hook();
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#endif
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}
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/*****************************************************************************/
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/* @brief Copy exception vectors to active exception table
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* @pre -
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* @param[in] ExcVecLabel - address of the core exception table
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* IntVecLabel - address of the interrupt vector table
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* Use BRS_DEFINE_ADDRESS_UNUSED for unused values
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* @param[out] -
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* @return -
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* @context Function is called from main@BrsMain at power on initialization
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*****************************************************************************/
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void BrsHw_ExceptionTable_Init(Brs_AddressOfConstType ExcVecLabel, Brs_AddressOfConstType IntVecLabel)
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{
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/* VBAR is Undefined/not available on ARMv7-R implementations ->
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Exception vector change is done via overwriting the exception vectors,
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which are placed at an offset of 0x20 bytes just behind the exception table start.
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See ARMv7_Cortex-R_BRS_Exception_Handling.pdf for details of the mechanism!
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*/
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int i;
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uint32 addressOfActiveExceptionTable;
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#if !defined (BRSHW_ARMCOMMON_COREEXCEPTIONS_AT_ADDRESS_0)
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uint32 runningCoreId;
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#endif
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#if defined (BRS_ENABLE_OS_MULTICORESUPPORT)
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uint32 coreFound;
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#endif
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#if defined (BRSHW_ARMCOMMON_COREEXCEPTIONS_AT_ADDRESS_0)
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addressOfActiveExceptionTable = 0x0;
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#else
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runningCoreId = BrsHw_GetCore();
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if (runningCoreId == BRSHW_INIT_CORE_ID)
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{
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# if defined (BRS_FIRST_EXECUTION_INSTANCE)
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addressOfActiveExceptionTable = ((uint32)&intvect_CoreExceptions);
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# else
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addressOfActiveExceptionTable = BRSHW_COREEXCEPTIONS_ADDRESS_OF_INIT_CORE;
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# endif
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}
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else
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{
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# if defined (BRS_ENABLE_OS_MULTICORESUPPORT)
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coreFound = 0;
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for (i=0; i < (BRS_CPU_CORE_AMOUNT-1); i++)
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{
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if (BrsHw_intvect_CoreExceptions_list[i].PhysicalCoreId == runningCoreId)
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{
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addressOfActiveExceptionTable = (uint32)(BrsHw_intvect_CoreExceptions_list[i].CoreExceptions);
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coreFound = 1;
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break;
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}
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}
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if (coreFound == 0)
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{
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BrsMainExceptionHandler(kBrsIllegalParameter, BRSERROR_MODULE_BRSHW, (uint16)(__LINE__));
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}
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# else
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BrsMainExceptionHandler(kBrsIllegalParameter, BRSERROR_MODULE_BRSHW, (uint16)(__LINE__));
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# endif /*BRS_ENABLE_OS_MULTICORESUPPORT*/
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}
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#endif /*else BRSHW_ARMCOMMON_COREEXCEPTIONS_AT_ADDRESS_0*/
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if(ExcVecLabel!=BRS_DEFINE_ADDRESS_UNUSED)
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{
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for (i=0; i<8; i++)
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{
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*((uint32*)(addressOfActiveExceptionTable+0x20+i*4)) = *(uint32*)(((uint32)ExcVecLabel)+0x20+i*4);
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}
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}
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#if defined (BRSHW_ECXEPTIONTABLE_INIT_POSTHOOK_AVAILABLE)
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BrsHw_ExceptionTable_Init_PostHook(ExcVecLabel, IntVecLabel);
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#endif
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}
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/*****************************************************************************/
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/* @brief This API is used for the BRS time measurement support to get a
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* default time value for all measurements with this platform to
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* be able to compare time measurements on different dates based
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* on this time result.
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* @pre Should be called with interrupts global disabled
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* @param[in] -
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* @param[out] -
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* @return -
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* @context Function is called from e.g. component testsuits for calibration
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*****************************************************************************/
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void BrsHwTime100NOP(void)
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{
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BRSHWNOP10();
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BRSHWNOP10();
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BRSHWNOP10();
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BRSHWNOP10();
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BRSHWNOP10();
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BRSHWNOP10();
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BRSHWNOP10();
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BRSHWNOP10();
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BRSHWNOP10();
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BRSHWNOP10();
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}
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#if !defined (BRSHW_PLATFORM_SPECIFIC_GETCORE_AVAILABLE)
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/*****************************************************************************/
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/* @brief This API is used to read the core ID of the actual running core
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* @pre -
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* @param[in] -
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* @param[out] -
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* @return Core ID of the actual running core
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* @context Function is e.g. called from main@BrsMain, to only call HW-init
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* code once, on the boot core.
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* In MultiCore setups, additional BRSHW_INIT_CORE_ID must be
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* declared inside BrsHw.h, to configure the proper core ID value
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* of that boot core.
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*****************************************************************************/
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uint32 BrsHw_GetCore(void)
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{
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#if (BRS_CPU_CORE_AMOUNT>1)
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uint32 id = 0;
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/* Read out the physical processor number (Multiprocessor affinity register (MPIDR))
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* 0 for Core0, Cluster0
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* 1 for Core1, Cluster0
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* 2 for Core0, Cluster1
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* 3 for Core1, Cluster1
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* 4 for Core0, Cluster2
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* 5 for Core1, Cluster2
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*/
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brsHwGetMpidr(id);
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return (((id & 0x0000FF00ul) >> 7) | (id & 3ul));
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#else
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/* Stub for SingleCore environments, always returns 0 */
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return 0u;
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#endif /*BRS_CPU_CORE_AMOUNT*/
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}
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#endif /*!BRSHW_PLATFORM_SPECIFIC_GETCORE_AVAILABLE*/
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