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FLEX-FORD-OBC-BM/Source/appl/ARMBrsHwIntTb_CortexR.c

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Flex OBC Initial Package creation
2026-03-19 11:49:16 +01:00
/**********************************************************************************************************************
* COPYRIGHT
* -------------------------------------------------------------------------------------------------------------------
* \verbatim
* Copyright (c) 2025 by Vector Informatik GmbH. All rights reserved.
*
* This software is copyright protected and proprietary to Vector Informatik GmbH.
* Vector Informatik GmbH grants to you only those rights as set out in the license conditions.
* All other rights remain with Vector Informatik GmbH.
* \endverbatim
* -------------------------------------------------------------------------------------------------------------------
* FILE DESCRIPTION
* -----------------------------------------------------------------------------------------------------------------*/
/** \file File: ARMBrsHwIntTb_CortexR.c
* Project: Vector Basic Runtime System
* Module: BrsHw for all platforms with ARM core Cortex-R
* Template: This file is reviewed according to Brs_Template@Implementation[1.03.12]
*
* \brief Description: This is a global, hardware-independent file for the ARM-BRS.
* It consists of the core exception table for Startup and a 2nd one to be copied into RAM
* for FBL projects.
*
* \attention Please note:
* The demo and example programs only show special aspects of the software. With regard to the fact
* that these programs are meant for demonstration purposes only, Vector Informatik liability shall be
* expressly excluded in cases of ordinary negligence, to the extent admissible by law or statute.
*********************************************************************************************************************/
/**********************************************************************************************************************
* REVISION HISTORY
* -------------------------------------------------------------------------------------------------------------------
* Refer to ARMBrsHw_CortexR.h.
*********************************************************************************************************************/
/**********************************************************************************************************************
* EXAMPLE CODE ONLY
* -------------------------------------------------------------------------------------------------------------------
* This Example Code is only intended for illustrating an example of a possible BSW integration and BSW configuration.
* The Example Code has not passed any quality control measures and may be incomplete. The Example Code is neither
* intended nor qualified for use in series production. The Example Code as well as any of its modifications and/or
* implementations must be tested with diligent care and must comply with all quality requirements which are necessary
* according to the state of the art before their use.
*********************************************************************************************************************/
#define ARMBRSHWINTTB_CORTEXR_SOURCE
/**********************************************************************************************************************
* INCLUDES
*********************************************************************************************************************/
#include "ARMBrsHw_CortexR.h"
/**********************************************************************************************************************
* CONFIGURATION CHECK
*********************************************************************************************************************/
#if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
#else
#error "Unknown compiler specified!"
#endif
/**********************************************************************************************************************
* PROTOTYPES OF LOCAL FUNCTIONS
*********************************************************************************************************************/
#if defined (BRS_FIRST_EXECUTION_INSTANCE)
BRS_ISR_KEYWORD void BrsHw_CoreExceptionHandler(void);
#endif
#if defined (BRS_ENABLE_OS_MULTICORESUPPORT)
BRS_ISR_KEYWORD void BrsHw_MultiCoreExceptionHandler(void);
BRS_LOCAL_FUNCTION_PROTOTYPE(intvect_Core1Exceptions)
# if (BRS_CPU_CORE_AMOUNT > 2)
BRS_LOCAL_FUNCTION_PROTOTYPE(intvect_Core2Exceptions)
# endif
# if (BRS_CPU_CORE_AMOUNT > 3)
BRS_LOCAL_FUNCTION_PROTOTYPE(intvect_Core3Exceptions)
# endif
# if (BRS_CPU_CORE_AMOUNT > 4)
BRS_LOCAL_FUNCTION_PROTOTYPE(intvect_Core4Exceptions)
# endif
# if (BRS_CPU_CORE_AMOUNT > 5)
BRS_LOCAL_FUNCTION_PROTOTYPE(intvect_Core5Exceptions)
# endif
# if (BRS_CPU_CORE_AMOUNT > 6)
BRS_LOCAL_FUNCTION_PROTOTYPE(intvect_Core6Exceptions)
# endif
# if (BRS_CPU_CORE_AMOUNT > 7)
BRS_LOCAL_FUNCTION_PROTOTYPE(intvect_Core7Exceptions)
# endif
# if (BRS_CPU_CORE_AMOUNT > 8)
#error "More than 8 cores actually not supported by ARMBrsHwIntTb_CortexR.c!"
# endif
#endif /*BRS_ENABLE_OS_MULTICORESUPPORT*/
#if defined (BRS_ENABLE_FBL_SUPPORT) && defined (BRS_FBL_EXCEPTIONTABLE_IN_RAM)
BRS_ISR_KEYWORD void BrsHw_CoreExceptionHandler_Ram(void);
#endif
extern void brsStartupEntry(void);
#if defined (BRS_FIRST_EXECUTION_INSTANCE)
/* This code is only needed for the first instance/executable in the system */
/********************************************************************************************
* *
* Startup Core Exception Handler *
* *
********************************************************************************************/
#define BRS_START_SEC_STARTUP_CODE
#include "Brs_MemMap.h"
BRS_ISR_KEYWORD void BrsHw_CoreExceptionHandler(void)
{
#if defined (BRSHW_BRSHW_COREEXCEPTIONHANDLER_CALLOUT)
BrsTestsuite_BrsHw_CoreExceptionHandler();
#endif
volatile uint8 Brs_Continue;
Brs_Continue = 0;
while (Brs_Continue == 0)
{
/* Set BrsMain_Continue to 1 to continue here.
* If the debugger is not able to show the stack properly, this mechanism can be used to find the
* source of the exception. */
}
}
#define BRS_STOP_SEC_STARTUP_CODE
#include "Brs_MemMap.h"
/********************************************************************************************
* *
* Startup Core Exception Table *
* *
********************************************************************************************/
# if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
# pragma clang section text = ".brsExcVect"
__attribute__((naked)) void intvect_CoreExceptions(void)
{
/* Exception Table */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 0: Reset */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 1: Undefined Instruction */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 2: SVCall */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 3: Abort Prefetch */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 4: Abort Data */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 5: Reserved */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 6: IRQ */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 7: FIQ */
}
# pragma clang section text = ""
/* Exception Vectors */
__attribute__((section(".brsExcVectConst"))) void (* const intvect_CoreExceptions_vectortable[])(void) = {
brsStartupEntry, /* Exception 0: Reset */
BrsHw_CoreExceptionHandler, /* Exception 1: Undefined Instruction */
BrsHw_CoreExceptionHandler, /* Exception 2: SVCall */
BrsHw_CoreExceptionHandler, /* Exception 3: Abort Prefetch */
BrsHw_CoreExceptionHandler, /* Exception 4: Abort Data */
BrsHw_CoreExceptionHandler, /* Exception 5: Reserved */
BrsHw_CoreExceptionHandler, /* Exception 6: IRQ */
BrsHw_CoreExceptionHandler /* Exception 7: FIQ */
};
/* Backup Exception Vectors */
__attribute__((section(".brsExcVectConst"))) void (* const intvect_CoreExceptions_vectortable_backup[])(void) = {
brsStartupEntry, /* Exception 0: Reset */
BrsHw_CoreExceptionHandler, /* Exception 1: Undefined Instruction */
BrsHw_CoreExceptionHandler, /* Exception 2: SVCall */
BrsHw_CoreExceptionHandler, /* Exception 3: Abort Prefetch */
BrsHw_CoreExceptionHandler, /* Exception 4: Abort Data */
BrsHw_CoreExceptionHandler, /* Exception 5: Reserved */
BrsHw_CoreExceptionHandler, /* Exception 6: IRQ */
BrsHw_CoreExceptionHandler /* Exception 7: FIQ */
};
# endif /*BRS_COMP_LLVMDIAB||BRS_COMP_LLVMTEXASINSTRUMENTS*/
#endif /*BRS_FIRST_EXECUTION_INSTANCE*/
#if defined (BRS_ENABLE_OS_MULTICORESUPPORT)
const ARMBrsHw_PhysicalCoreId_CoreExceptions_MappingType BrsHw_intvect_CoreExceptions_list[BRS_CPU_CORE_AMOUNT-1] = {
{1, intvect_Core1Exceptions}
# if (BRS_CPU_CORE_AMOUNT > 2)
,{2, intvect_Core2Exceptions}
# endif
# if (BRS_CPU_CORE_AMOUNT > 3)
,{3, intvect_Core3Exceptions}
# endif
# if (BRS_CPU_CORE_AMOUNT > 4)
,{4, intvect_Core4Exceptions}
# endif
# if (BRS_CPU_CORE_AMOUNT > 5)
,{5, intvect_Core5Exceptions}
# endif
# if (BRS_CPU_CORE_AMOUNT > 6)
,{6, intvect_Core6Exceptions}
# endif
# if (BRS_CPU_CORE_AMOUNT > 7)
,{7, intvect_Core7Exceptions}
# endif
};
/********************************************************************************************
* *
* MultiCore Exception Handler *
* *
********************************************************************************************/
#if defined (BRS_FIRST_EXECUTION_INSTANCE)
#define BRS_START_SEC_STARTUP_CODE
#include "Brs_MemMap.h"
#endif
BRS_ISR_KEYWORD void BrsHw_MultiCoreExceptionHandler(void)
{
#if defined (BRSHW_BRSHW_MULTICOREEXCEPTIONHANDLER_CALLOUT)
BrsTestsuite_BrsHw_MultiCoreExceptionHandler();
#endif
volatile uint8 Brs_Continue;
Brs_Continue = 0;
while (Brs_Continue == 0)
{
/* Set Brs_Continue to 1 to continue here.
* If the debugger is not able to show the stack properly, this mechanism can be used to find the
* source of the exception. */
}
}
#if defined (BRS_FIRST_EXECUTION_INSTANCE)
#define BRS_STOP_SEC_STARTUP_CODE
#include "Brs_MemMap.h"
#endif
/********************************************************************************************
* *
* Core 1 Exception Table *
* *
********************************************************************************************/
# if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
# pragma clang section text = ".brsExcVect1"
__attribute__((naked)) void intvect_Core1Exceptions(void)
{
/* Exception Table */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 0: Reset */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 1: Undefined Instruction */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 2: SVCall */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 3: Abort Prefetch */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 4: Abort Data */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 5: Reserved */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 6: IRQ */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 7: FIQ */
}
# pragma clang section text = ""
/* Exception Vectors */
__attribute__((section(".brsExcVect1Const"))) void (* const intvect_Core1Exceptions_vectortable[])(void) = {
brsStartupEntry, /* Exception 0: Reset */
BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
};
/* Backup Exception Vectors */
__attribute__((section(".brsExcVect1Const"))) void (* const intvect_Core1Exceptions_vectortable_backup[])(void) = {
brsStartupEntry, /* Exception 0: Reset */
BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
};
# endif /*BRS_COMP_LLVMDIAB||BRS_COMP_LLVMTEXASINSTRUMENTS*/
# if (BRS_CPU_CORE_AMOUNT > 2)
/********************************************************************************************
* *
* Core 2 Exception Table *
* *
********************************************************************************************/
# if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
# pragma clang section text = ".brsExcVect2"
__attribute__((naked)) void intvect_Core2Exceptions(void)
{
/* Exception Table */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 0: Reset */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 1: Undefined Instruction */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 2: SVCall */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 3: Abort Prefetch */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 4: Abort Data */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 5: Reserved */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 6: IRQ */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 7: FIQ */
}
# pragma clang section text = ""
/* Exception Vectors */
__attribute__((section(".brsExcVect2Const"))) void (* const intvect_Core2Exceptions_vectortable[])(void) = {
brsStartupEntry, /* Exception 0: Reset */
BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
};
/* Backup Exception Vectors */
__attribute__((section(".brsExcVect2Const"))) void (* const intvect_Core2Exceptions_vectortable_backup[])(void) = {
brsStartupEntry, /* Exception 0: Reset */
BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
};
# endif /*BRS_COMP_LLVMDIAB||BRS_COMP_LLVMTEXASINSTRUMENTS*/
# endif /*BRS_CPU_CORE_AMOUNT > 2*/
# if (BRS_CPU_CORE_AMOUNT > 3)
/********************************************************************************************
* *
* Core 3 Exception Table *
* *
********************************************************************************************/
# if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
# pragma clang section text = ".brsExcVect3"
__attribute__((naked)) void intvect_Core3Exceptions(void)
{
/* Exception Table */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 0: Reset */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 1: Undefined Instruction */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 2: SVCall */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 3: Abort Prefetch */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 4: Abort Data */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 5: Reserved */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 6: IRQ */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 7: FIQ */
}
# pragma clang section text = ""
/* Exception Vectors */
__attribute__((section(".brsExcVect3Const"))) void (* const intvect_Core3Exceptions_vectortable[])(void) = {
brsStartupEntry, /* Exception 0: Reset */
BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
};
/* Backup Exception Vectors */
__attribute__((section(".brsExcVect3Const"))) void (* const intvect_Core3Exceptions_vectortable_backup[])(void) = {
brsStartupEntry, /* Exception 0: Reset */
BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
};
# endif /*BRS_COMP_LLVMDIAB||BRS_COMP_LLVMTEXASINSTRUMENTS*/
# endif /*BRS_CPU_CORE_AMOUNT > 3*/
# if (BRS_CPU_CORE_AMOUNT > 4)
/********************************************************************************************
* *
* Core 4 Exception Table *
* *
********************************************************************************************/
# if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
# pragma clang section text = ".brsExcVect4"
__attribute__((naked)) void intvect_Core4Exceptions(void)
{
/* Exception Table */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 0: Reset */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 1: Undefined Instruction */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 2: SVCall */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 3: Abort Prefetch */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 4: Abort Data */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 5: Reserved */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 6: IRQ */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 7: FIQ */
}
# pragma clang section text = ""
/* Exception Vectors */
__attribute__((section(".brsExcVect4Const"))) void (* const intvect_Core4Exceptions_vectortable[])(void) = {
brsStartupEntry, /* Exception 0: Reset */
BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
};
/* Backup Exception Vectors */
__attribute__((section(".brsExcVect4Const"))) void (* const intvect_Core4Exceptions_vectortable_backup[])(void) = {
brsStartupEntry, /* Exception 0: Reset */
BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
};
# endif /*BRS_COMP_LLVMDIAB||BRS_COMP_LLVMTEXASINSTRUMENTS*/
# endif /*BRS_CPU_CORE_AMOUNT > 4*/
# if (BRS_CPU_CORE_AMOUNT > 5)
/********************************************************************************************
* *
* Core 5 Exception Table *
* *
********************************************************************************************/
# if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
# pragma clang section text = ".brsExcVect5"
__attribute__((naked)) void intvect_Core5Exceptions(void)
{
/* Exception Table */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 0: Reset */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 1: Undefined Instruction */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 2: SVCall */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 3: Abort Prefetch */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 4: Abort Data */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 5: Reserved */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 6: IRQ */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 7: FIQ */
}
# pragma clang section text = ""
/* Exception Vectors */
__attribute__((section(".brsExcVect5Const"))) void (* const intvect_Core5Exceptions_vectortable[])(void) = {
brsStartupEntry, /* Exception 0: Reset */
BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
};
/* Backup Exception Vectors */
__attribute__((section(".brsExcVect5Const"))) void (* const intvect_Core5Exceptions_vectortable_backup[])(void) = {
brsStartupEntry, /* Exception 0: Reset */
BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
};
# endif /*BRS_COMP_LLVMDIAB||BRS_COMP_LLVMTEXASINSTRUMENTS*/
# endif /*BRS_CPU_CORE_AMOUNT > 5*/
# if (BRS_CPU_CORE_AMOUNT > 6)
/********************************************************************************************
* *
* Core 6 Exception Table *
* *
********************************************************************************************/
# if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
# pragma clang section text = ".brsExcVect6"
__attribute__((naked)) void intvect_Core6Exceptions(void)
{
/* Exception Table */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 0: Reset */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 1: Undefined Instruction */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 2: SVCall */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 3: Abort Prefetch */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 4: Abort Data */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 5: Reserved */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 6: IRQ */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 7: FIQ */
}
# pragma clang section text = ""
/* Exception Vectors */
__attribute__((section(".brsExcVect6Const"))) void (* const intvect_Core6Exceptions_vectortable[])(void) = {
brsStartupEntry, /* Exception 0: Reset */
BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
};
/* Backup Exception Vectors */
__attribute__((section(".brsExcVect6Const"))) void (* const intvect_Core6Exceptions_vectortable_backup[])(void) = {
brsStartupEntry, /* Exception 0: Reset */
BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
};
# endif /*BRS_COMP_LLVMDIAB||BRS_COMP_LLVMTEXASINSTRUMENTS*/
# endif /*BRS_CPU_CORE_AMOUNT > 6*/
# if (BRS_CPU_CORE_AMOUNT > 7)
/********************************************************************************************
* *
* Core 7 Exception Table *
* *
********************************************************************************************/
# if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
# pragma clang section text = ".brsExcVect7"
__attribute__((naked)) void intvect_Core7Exceptions(void)
{
/* Exception Table */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 0: Reset */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 1: Undefined Instruction */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 2: SVCall */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 3: Abort Prefetch */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 4: Abort Data */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 5: Reserved */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 6: IRQ */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 7: FIQ */
}
# pragma clang section text = ""
/* Exception Vectors */
__attribute__((section(".brsExcVect7Const"))) void (* const intvect_Core7Exceptions_vectortable[])(void) = {
brsStartupEntry, /* Exception 0: Reset */
BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
};
/* Backup Exception Vectors */
__attribute__((section(".brsExcVect7Const"))) void (* const intvect_Core7Exceptions_vectortable_backup[])(void) = {
brsStartupEntry, /* Exception 0: Reset */
BrsHw_MultiCoreExceptionHandler, /* Exception 1: Undefined Instruction */
BrsHw_MultiCoreExceptionHandler, /* Exception 2: SVCall */
BrsHw_MultiCoreExceptionHandler, /* Exception 3: Abort Prefetch */
BrsHw_MultiCoreExceptionHandler, /* Exception 4: Abort Data */
BrsHw_MultiCoreExceptionHandler, /* Exception 5: Reserved */
BrsHw_MultiCoreExceptionHandler, /* Exception 6: IRQ */
BrsHw_MultiCoreExceptionHandler /* Exception 7: FIQ */
};
# endif /*BRS_COMP_LLVMDIAB||BRS_COMP_LLVMTEXASINSTRUMENTS*/
# endif /*BRS_CPU_CORE_AMOUNT > 7*/
#endif /*BRS_ENABLE_OS_MULTICORESUPPORT*/
#if defined (BRS_ENABLE_FBL_SUPPORT) && defined (BRS_FBL_EXCEPTIONTABLE_IN_RAM)
/********************************************************************************************
* *
* Core Exception Handler in RAM *
* *
********************************************************************************************/
#define BRS_START_SEC_RAM_CODE
#include "Brs_MemMap.h"
BRS_ISR_KEYWORD void BrsHw_CoreExceptionHandler_Ram(void)
{
#if defined (BRSHW_BRSHW_COREEXCEPTIONHANDLER_RAM_CALLOUT)
BrsTestsuite_BrsHw_CoreExceptionHandler_Ram();
#endif
volatile uint8 Brs_Continue;
Brs_Continue = 0;
while (Brs_Continue == 0)
{
/* Set Brs_Continue to 1 to continue here.
* If the debugger is not able to show the stack properly, this mechanism can be used to find the
* source of the exception. */
}
}
#define BRS_STOP_SEC_RAM_CODE
#include "Brs_MemMap.h"
/********************************************************************************************
* *
* Core Exception Table in RAM *
* *
********************************************************************************************/
# if !defined (BRS_FIRST_EXECUTION_INSTANCE)
#error "If this executable is not first execution instance, reset vector must be manually set in RAM exception table to entry address!"
/* Replace brsStartupEntry in the RAM exception table with, e.g., 0x80, as this linker symbol will not exist in this case. Then, comment out the error message above. */
# endif
# if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
# pragma clang section text = ".brsExcVectRam"
__attribute__((naked)) void intvect_CoreExceptions_Ram(void)
{
/* Exception Table */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 0: Reset */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 1: Undefined Instruction */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 2: SVCall */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 3: Abort Prefetch */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 4: Abort Data */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 5: Reserved */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 6: IRQ */
__asm(" ldr pc,[pc,#0x18] "); /* Exception 7: FIQ */
}
# pragma clang section text = ""
/* Exception Vectors */
__attribute__((section(".brsExcVectRamConst"))) void (* const intvect_CoreExceptions_Ram_Vectortable[])(void) = {
brsStartupEntry, /* Exception 0: Reset */
BrsHw_CoreExceptionHandler_Ram, /* Exception 1: Undefined Instruction */
BrsHw_CoreExceptionHandler_Ram, /* Exception 2: SVCall */
BrsHw_CoreExceptionHandler_Ram, /* Exception 3: Abort Prefetch */
BrsHw_CoreExceptionHandler_Ram, /* Exception 4: Abort Data */
BrsHw_CoreExceptionHandler_Ram, /* Exception 5: Reserved */
BrsHw_CoreExceptionHandler_Ram, /* Exception 6: IRQ */
BrsHw_CoreExceptionHandler_Ram /* Exception 7: FIQ */
};
# endif /*BRS_COMP_LLVMDIAB||BRS_COMP_LLVMTEXASINSTRUMENTS*/
#endif /*BRS_ENABLE_FBL_SUPPORT&&BRS_FBL_EXCEPTIONTABLE_IN_RAM*/