/**********************************************************************************************************************
 *  COPYRIGHT
 *  -------------------------------------------------------------------------------------------------------------------
 *  \verbatim
 *  Copyright (c) 2025 by Vector Informatik GmbH.                                                  All rights reserved.
 *
 *                This software is copyright protected and proprietary to Vector Informatik GmbH.
 *                Vector Informatik GmbH grants to you only those rights as set out in the license conditions.
 *                All other rights remain with Vector Informatik GmbH.
 *  \endverbatim
 *  -------------------------------------------------------------------------------------------------------------------
 *  FILE DESCRIPTION
 *  -----------------------------------------------------------------------------------------------------------------*/
/** \file  File:  ARMBrsHw_CortexR.h
 *      Project:  Vector Basic Runtime System
 *       Module:  BrsHw for all platforms with ARM core Cortex-R
 *
 *  \brief Description:  This is a global, platform-independent header file for the ARM-BRS.
 *                       This file includes all non-platform dependent functions.
 *                       All the (platform depending) rest needs to be defined in BrsHw.c
 *
 *  \attention Please note:
 *    The demo and example programs only show special aspects of the software. With regard to the fact
 *    that these programs are meant for demonstration purposes only, Vector Informatik liability shall be
 *    expressly excluded in cases of ordinary negligence, to the extent admissible by law or statute.
 *********************************************************************************************************************/

/**********************************************************************************************************************
 *  REVISION HISTORY
 *  -------------------------------------------------------------------------------------------------------------------
 *  Version   Date        Author  Change Id      Description
 *  -------------------------------------------------------------------------------------------------------------------
 *  01.00.00  2020-15-19  visbwa                 New branch for vBaseEnv 2.0, based on zBrs_ArmCommon ARMBrsHw_CortexA.c 4.07.01 and ARMStartup_CortexA.c 1.11.01;
 *                                               updated vLinkGen define and struct names to new vLinkGen 2.0 naming schema in ARMStartup_CortexA.c
 *  01.00.01  2020-06-08  visbwa                 Fixed support for Tasking compiler and usage of struct vLinkGen_MemArea (vLinkGen_ZeroInit_Early_Blocks,
 *                                               vLinkGen_ZeroInit_Early_Groups) -> size is 16Byte per entry in ARMStartup_CortexA.c
 *  01.00.02  2020-06-09  visbwa                 Fixed IAR code to load stack symbols in ARMStartup_CortexA.c
 *  01.00.03  2020-07-03  visbwa                 Added disabling of abort handler and VIC for TDA4VM88@TI; added support for up to 6 cores in ARMStartup_CortexA.c
 *  01.01.00  2020-09-18  visbwa                 Review according to Brs_Template 1.01.00
 *  01.01.01  2020-10-21  vishci                 Fixed BRS_ISR_KEYWORD of Arm5, Gnu and Iar compiler abstraction in ARMBrsHw_CortexA.h; update to
 *                                               Brs_Template 1.01.01; removed AUTHOR IDENTITY; added new file ARMBrsHwIntTb_CortexR.c for FBL projects w/o OS
 *  01.01.02  2020-10-23  visbwa                 Renamed exception vector table according to Brs_Template in ARMBrsHwIntTb_CortexR.c
 *  01.01.03  2020-10-28  visbwa                 No changes in sourcecode, only within ALM package
 *  01.01.04  2020-11-09  visbwa                 No changes in sourcecode, only within ALM package
 *  01.01.05  2020-11-12  visdri                 Support Jacinto7 Cortex-R cores by merging the Jacinto7 startup code provided by TI (disable TCM and call mpu_init
 *                                               for Jacinto7 derivative) and fixed activation of FPU + initialization order (switch to system mode after FPU init)
 *                                               in ARMStartup_CortexA.c
 *  01.01.06  2020-12-07  visjhr                 Added support for TPR12 derivative and disabling of abort handler and VIC for it
 *  01.01.07  2021-01-14  visbwa                 Fixed BRANCH to startup_block_zero_init_loop_start for ARM compilers in ARMStartup_CortexA.c
 *  01.01.08  2021-03-05  visdri                 Removed Tasking and HighTec from list of supported compilers,
 *                                               removed BRS_EXTERN_BRANCH (separation to BRS_BRANCH not needed on Cortex-A/R) and
 *                                               fixed branches to stack pointer init routines for MultiCore in ARMStartup_CortexA.c
 *  01.01.09  2021-03-08  visbwa                 Fixed IAR encapsulation of Brs_IarLoadCore0Id (only for MultiCore) and branch extern in ARMStartup_CortexA.c
 *  01.02.00  2021-02-02  vismaa                 Added BrsHw_GetCore() and macros BRS_READ_COREID + brsHwGetMpidr
 *            2021-03-09  visbwa                 Renamed all files from ARMBrsHw_CortexA into ARMBrsHw_CortexR; update to Brs_Template 1.02.00; moved revision
 *                                               history of all .c and .h files into ARMBrsHw_CortexR.h; added SingleCore stubs for Read_COREID (always return 0)
 *  01.02.01  2021-03-18  vismaa                 Fixed memory initialization process in ARMStartup_CortexR.c to work properly in MultiCore environments
 *  01.03.00  2021-04-20  vishci                 Added LlvmDiab compiler support, fixed IAR compiler support in FBL CoreExceptionTable
 *            2021-05-04  visbwa                 Review, generalized BrsHwDisableInterruptAtPowerOn(), removed duplicates in TI compiler abstraction
 *  01.03.01  2021-05-11  visbwa                 Fixed brsExcVect section for Arm6 and LlvmDiab in ARMBrsHwIntTb_CortexR.c
 *  01.03.02  2021-07-28  visjhr                 Fixed bug in brsHwGetMpidr(c) for GCC compilers
 *  01.03.03  2021-08-03  visjhr                 Adapted bugfix of brsHwGetMpidr(c) for LLVMDIAB compiler
 *  01.03.04  2021-09-21  visbpz                 Adaptation for IAR
 *  01.04.00  2021-10-18  vishci                 added LLVMTEXASINSTRUMENTS compiler support
 *  01.04.01  2021-10-20  visbpz                 Fix for 8 byte aligned ECC initialization
 *            2021-10-25  visbwa                 Added usage of alignment parameter to distinguish between 4-Byte and 8-Byte init
 *  01.04.02  2022-03-01  visbwa  ESCAN00111389  Fixed zero_init loops in ARMStartup_CortexR.c, renamed area_zero_init to group_zero_init,
 *                                ESCAN00111390  introduced BRS_BRANCH_GREATER_THAN_OR_EQUAL
 *  01.04.03  2022-03-14  visbwa  ESCAN00111478  StartupCode is not mapped into specific section "brsStartup" for Arm6 compiler (ARMStartup_CortexR.c),
 *                                ESCAN00111480  StartupCode is using ARM_LIB_STACK instead of STACK_C0 to initialize stackpointer during startup
 *                                               (ARMStartup_CortexR.c); removed useless abstraction for asm in ARMBrsHw_CortexR.c; removed unused
 *                                               BRS_SECTION_DATA fragments from some compiler abstractions; replaced BRS_DUMMY_FUNC by Startup_Handler_ASM()
 *                                               (adjustment with Cortex-M code)
 *  01.04.04  2022-04-06  virmid                 Support for TDA4VE derivative
 *  02.00.00  2022-03-17  visjhr                 Update to Brs_Template 1.03.04
 *            2022-05-23  visbwa                 Review, harmonized with Implementation_CortexR52; call of __mpu_init moved to BrsHwEarlyInitPowerOn() of
 *                                               platform-specific BrsHw packages; fixed encapsulation of _start (alternative start symbol for OS)
 *            2022-07-22  visjhr                 Updated ARM5 implementation of BRS_READ_COREID; BRS_READ_COREID and BrsHw_GetCore() overloadable in platform
 *                                               specific BrsHw; changed implementation of BRS_READ_COREID that only AFF0 will be used for core id
 *            2022-07-25  visbwa                 Review; Removed platform specific code from BrsHwDisableInterruptAtPowerOn() and StartupCode;
 *                                               Introduced BrsHwDisableInterruptAtPowerOn_Hook()
 *  02.00.01  2022-07-26  visbwa                 Fixed Arm5 assembly abstraction, introduced usage of BRS_ENABLE_OS_STUB for Arm5/Arm6
 *  02.00.02  2022-07-26  visjhr                 Fixed exception tables for LLVM DIAB and LLVM TI compiler
 *  02.00.03  2022-08-04  visrgm                 Added BRSHW_PRE_ASM_STARTUP_HOOK_AVAILABLE define to ARMStartup_CortexR.c
 *  02.00.04  2022-08-11  mhu                    Fixed Brs_IarLoadCoreConfigSizeSymbol implementation
 *            2022-08-12  visqli                 Introduced BrsHw_ExceptionTable_Init_PostHook in BrsHw_ExceptionTable_Init
 *  02.00.05  2022-09-07  visjhr                 Added code for restoring default Exception Table code on startup (identical for all exceptions)
 *  02.01.00  2022-09-21  visjhr                 Added exception tables for max 8 cores in multicore setups, updated calculation of active exception table address
 *                                               during startup, special implementation if core exception table is located at address 0x0
 *  02.01.01  2022-10-10  mhu                    Fixed multicore implementation of BRS_READ_COREID and BrsHw_GetCore(); updated declartions and definitions of
 *                                               intvect_CoreXExceptions for IAR; adapted the position of BRS_READ_COREID to avoid overwrite of R0 in
 *                                               ARMStartup_CortexR.c
 *                        visbwa                 Review, introduced BRS_LOCAL_FUNCTION_PROTOTYPE
 *  02.01.02  2023-02-01  mhu                    Fixed brsHwGetMpidr() definition with IAR compiler for multicore usecase
 *  02.02.00  2023-03-02  virjas                 Changed syntax of brsHwGetMpidr asm macro fro Llvm and IAR compiler to be c99 (__asm)
 *            2023-05-23  visbwa                 Update to Brs_Template 1.03.09: mapping of BrsHw_CoreExceptionHandler() into startup code section in
 *                                               ARMBrsHwIntTb_CortexR.c
 *  02.02.01  2023-05-25  visdri                 Fix multicore exception tables in ARMBrsHwIntTb_CortexR.c for TI compiler.
 *  02.02.02  2023-06-05  visbwa                 Introduction of BrsHw_MultiCoreExceptionHandler() as single and independent handler for all additional cores;
 *                                               mapped into startup code section in ARMBrsHwIntTb_CortexR.c
 *  02.03.00  2023-06-28  visdri                 Set SCTLR.TE bit in startup code to enter exceptions in ARM state
 *  02.04.00  2024-08-01  vishci  BASEENV-12178  Unify naming of coreexception table in RAM for FBL usecase
 *  02.04.01  2024-09-05  vishci                 Fixed core exception intvect_CoreExceptions_Ram_Vectortable bug
 *  02.05.00  2024-09-16  kal     BASEENV-12584  Implemented cache invalidation for all ARMv7-R cores; bugfix for ARM5 compiler
 *  02.05.01  2024-11-22  kal     BASEENV-12761  Fixed bad instruction in Arm6 Exception table
 *  02.05.02  2024-12-11  mhu                    Fixed #pragma grammar for Arm6 compiler
 *  02.05.03  2025-01-15  mhu                    Fixed BRSHW_DEFINE_STARTUP_STACK define for Arm6 compiler
 *  02.05.04  2025-01-31  vismaa  BASEENV-13175  Clearing SCTLR V-Bit, assures base location of exception registers is 0x0000_0000
 *  02.05.05  2025-03-28  visbwa  BASEENV-13195  Added compiler error for non-first execution instance and exception table in RAM combination
 *********************************************************************************************************************/

#ifndef _ARMBRSHW_CORTEXR_H_
#define _ARMBRSHW_CORTEXR_H_

/**********************************************************************************************************************
 *  MODULE VERSION
 *********************************************************************************************************************/
/*
 * Description: This is the BrsHw main and bug fix version. The version numbers are BCD coded.
 *              E.g. a main version of 1.23 is coded with 0x0123, a bug fix version of 9 is coded 0x09.
 */
#define ARMBRSHW_CORTEXR_VERSION        0x0205u
#define ARMBRSHW_CORTEXR_BUGFIX_VERSION 0x05u

/**********************************************************************************************************************
 *  INCLUDES
 *********************************************************************************************************************/
/*
 * Description: The BrsCfg header is used to configure different types of
 *              tests and system setups. Therefore it must be included first
 *              in each BRS and test module.
 *              This file is part of the BRS.
 */
#include "vBrsCfg.h"

#include "BrsMain.h"

/**********************************************************************************************************************
 *  CONFIGURATION CHECK
 *********************************************************************************************************************/
/* Configuration checks performed within platform specific code (BrsHw) */

/**********************************************************************************************************************
 *  GLOBAL TYPE DEFINITIONS
 *********************************************************************************************************************/
#if defined (BRS_ENABLE_OS_MULTICORESUPPORT)
typedef struct
{
  uint32 PhysicalCoreId;
  void (*CoreExceptions)();
}ARMBrsHw_PhysicalCoreId_CoreExceptions_MappingType;
#endif /*BRS_ENABLE_OS_MULTICORESUPPORT*/

/**********************************************************************************************************************
 *  GLOBAL CONSTANT MACROS
 *********************************************************************************************************************/
/*
 * Description: Macro for access to IO addresses
 */
#define BRSHW_IOS(type, address) (*((volatile type *)(address)))

#define BRSHWNOP10() do { \
  __asm(" NOP");          \
  __asm(" NOP");          \
  __asm(" NOP");          \
  __asm(" NOP");          \
  __asm(" NOP");          \
  __asm(" NOP");          \
  __asm(" NOP");          \
  __asm(" NOP");          \
  __asm(" NOP");          \
  __asm(" NOP");          \
  } while(0)

/* 
 * Description: Macros used in vBRS generated vBrs_Lcfg.c.
 */
  #define BRSHW_DEFINE_STARTUP_STACK(x)  _STACK_C##x##_LIMIT

  /* No separate ExcVec table on cortexR! OS is defining one interrupt table for exceptions + interrupts */
  #define BRSHW_DEFINE_EXCVEC(x)         _OS_EXCVEC_CORE##x##_CODE_START
  #define BRSHW_DEFINE_INTVEC(x)         _OS_EXCVEC_CORE##x##_CODE_START /* just as dummy to compile vBrs_Lcfg.c, not used in BrsHw_ExceptionTable_Init() */

/* Special value, needed for SingleCore UseCase w/o OS (e.g. FBL). vBRS will generate "BRSHW_DEFINE_STARTUP_STACK(BRSHW_INIT_CORE_ID)"
   for this. Configure here the valid value for the StartupStack pointer label of the boot core */
#define _STACK_CBRSHW_INIT_CORE_ID_LIMIT _STACK_C0_LIMIT /* this macro is not used with Arm5/Arm6 compilers */

/**********************************************************************************************************************
 * Compiler abstraction
 *********************************************************************************************************************/
#if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
  #define ___asm(c)                __asm_(c)
  #define __asm_(c)                __asm(#c);
  #define __as1(c, d)              __as1_(c, d)
  #define __as1_(c, d)             __asm( #c " , " #d);
  #define __as2(c, d, e)           __as2_(c, d, e)
  #define __as2_(c, d, e)          __asm( #c " , " #d " , " #e);
  #define __as3(c, d, e, f)        __as3_(c, d, e, f)
  #define __as3_(c, d, e, f)       __asm( #c " , " #d " , " #e " , " #f);
  #define __as4(c, d, e, f, g)     __as4_(c, d, e, f, g)
  #define __as4_(c, d, e, f, g)    __asm( #c " , " #d " , " #e " , " #f  " , " #g);
  #define __as5(c, d, e, f, g, h)  __as5_(c, d, e, f, g, h)
  #define __as5_(c, d, e, f, g, h) __asm( #c " , " #d " , " #e " , " #f  " , " #g " , " #h);

  #define BRS_MULTILINE_ASM_BEGIN()
  #define BRS_MULTILINE_ASM_END()

  #define BRS_ASM_EQU(Label, Value) __as1(.equ Label, Value)

  #define BRS_ISR_KEYWORD __attribute__ ((interrupt("IRQ")))

  #define BRS_SECTION_CODE(c)     __as1(.section .c , "ax" )

  #define BRS_GLOBAL(c)                   ___asm(.globl c)
  #define BRS_LOCAL_PROTOTYPE(c)          void c (void);
  #define BRS_LOCAL_FUNCTION_PROTOTYPE(c) void c (void);
  #define BRS_LABEL(c)                    ___asm(c:)
  #define BRS_GLOBAL_END()

# if defined (BRS_COMP_LLVMTEXASINSTRUMENTS)
# define BRS_EXPORT(Label)        ___asm(.global Label)  /* Causes the identifier Label to be visible externally */
# endif

  /* Unconditional branch to c */
  #define BRS_BRANCH(c)           ___asm(B c)
  #define BRS_EXTERN_BRANCH(c)    ___asm(B c)

  /* Branch to e if c and d are equal */
  #define BRS_BRANCH_EQUAL(c,d,e)  __as1(CMP c, d) \
                                   ___asm(BEQ e)

  /* Branch to e if c and d are NOT equal */
  #define BRS_BRANCH_NOT_EQUAL(c,d,e)  __as1(CMP c, d) \
                                       ___asm(BNE e)

  /* Branch to e if c is greater than d*/
  #define BRS_BRANCH_GREATER_THAN(c,d,e)  __as1(CMP c, d) \
                                         ___asm(BGT e)

  /* Branch to e if c is greater or equal than d */
  #define BRS_BRANCH_GREATER_THAN_OR_EQUAL(c,d,e)  __as1(CMP c, d) \
                                                   ___asm(BGE e)

# if (BRS_CPU_CORE_AMOUNT>1)
#  if !defined (BRSHW_PLATFORM_SPECIFIC_GETCORE_AVAILABLE)
  #define BRS_READ_COREID(c) __asm( "mrc p15" "," "#0" "," #c "," "c0" ","  "c0" "," "#5" );  \
                             __asm( "and r9 " "," #c "," "#255" );  \
                             __asm( "and " #c "," #c "," "#0xFF00" ); \
                             __asm( "orr " #c "," "r9" "," #c "," "lsr #7" );

  /* Multiprocessor affinity (MPIDR) */
  #define brsHwGetMpidr(c) __asm("MRC p15, 0, %0, c0, c0, 5" : "=r" (c) :)
#  endif /*!BRSHW_PLATFORM_SPECIFIC_GETCORE_AVAILABLE*/

# else
  /* Stub for SingleCore environments, always returns 0 */
  #define BRS_READ_COREID(c) __as1(MOV c, 0)
# endif /*BRS_CPU_CORE_AMOUNT*/

#else
  #error "Compiler not yet supported"
#endif /*BRS_COMP_x*/

/**********************************************************************************************************************
 *  BrsHW configuration
 *********************************************************************************************************************/

/**********************************************************************************************************************
 *  GLOBAL VARIABLES
 *********************************************************************************************************************/

/**********************************************************************************************************************
 *  GLOBAL FUNCTION PROTOTYPES
 *********************************************************************************************************************/

/*****************************************************************************/
/* @brief      Disable the global system interrupt.
 * @pre        Must be the first function call in main@BrsMain
 * @param[in]  -
 * @param[out] -
 * @return     -
 * @context    Function is called from main@BrsMain at power on initialization
 *****************************************************************************/
void BrsHwDisableInterruptAtPowerOn(void);

/*****************************************************************************/
/* @brief      Copy exception vectors to active exception table
 * @pre        -
 * @param[in]  ExcVecLabel - address of the core exception table
 *             IntVecLabel - address of the interrupt vector table
 *             Use BRS_DEFINE_ADDRESS_UNUSED for unused values
 * @param[out] -
 * @return     -
 * @context    Function is called from main@BrsMain at power on initialization
 *****************************************************************************/
void BrsHw_ExceptionTable_Init(Brs_AddressOfConstType, Brs_AddressOfConstType);

/*****************************************************************************/
/* @brief      This API is used for the BRS time measurement support to get a
 *             default time value for all measurements with this platform to
 *             be able to compare time measurements on different dates based
 *             on this time result.
 * @pre        Should be called with interrupts global disabled
 * @param[in]  -
 * @param[out] -
 * @return     -
 * @context    Function is called from e.g. component testsuits for calibration
 *****************************************************************************/
void BrsHwTime100NOP(void);

#if !defined (BRSHW_PLATFORM_SPECIFIC_GETCORE_AVAILABLE)
/*****************************************************************************/
/* @brief      This API is used to read the core ID of the actual running core
 * @pre        -
 * @param[in]  -
 * @param[out] -
 * @return     Core ID of the actual running core
 * @context    Function is e.g. called from main@BrsMain, to only call HW-init
 *             code once, on the boot core.
 *             In MultiCore setups, additional BRSHW_INIT_CORE_ID must be
 *             declared inside BrsHw.h, to configure the proper core ID value
 *             of that boot core.
 *****************************************************************************/
uint32 BrsHw_GetCore(void);
#endif /*!BRSHW_PLATFORM_SPECIFIC_GETCORE_AVAILABLE*/

#endif /*_ARMBRSHW_CORTEXR_H_*/
